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This research aims to design and evaluate a lightweight microcontroller based on the RISC-V architecture with added custom features.

July 20, 2026Discover ComputingOpen Access

Design and implementation of a single-cycle RISC-V microcontroller with custom ISA extensions and peripheral integration

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Randomized trial demonstrates improved performance and efficiency in RISC-V microcontrollers, indicating viable embedded application solutions.

This research aims to design and evaluate a lightweight microcontroller based on the RISC-V architecture with added custom features.
Designed a single-cycle RISC-V microcontroller with a custom instruction set and peripheral integration.
Synthesized the design using Verilog HDL and implemented it on Xilinx Artix-7 FPGA.
Verified functional correctness using standard RISC-V compliance tests.
Experimental results show improved execution efficiency and reduced instruction count.
Trade-offs demonstrate favorable performance and power efficiency compared to existing RISC-V soft cores.
Integration of major peripherals like UART and GPIO simplifies system development.

Srivastava et al. (2026) studied this question.

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Randomized trial demonstrates improved performance and efficiency in RISC-V microcontrollers, indicating viable embedded application solutions.