Si Interposer With Cu TSVs on Cu Substrate Thermally and Electrically Anchoring Qubit Chips in Millikelvin Assembly

A cryo-Si interposer uses a 0.18 μm CMOS technology for active circuits and passive routings for mounting qubit chips on the frontside and equips Cu TSVs with 20 μm thickness and Cu pillars with 20 μm height on the backside through via-last wafer-level processing. The Si interposer is diced and then Cu-Cu bonded to Cu plate or Cu substrate in a chip-to-chip way, to establish thermally and electrically anchoring of qubits to a cryogenic heat reservoir at the reference voltage in a refrigerator. The proposed cryo-Si interposer confirmed its structural stability after cryogenic thermal cycles.