Process Challenges in Thin Wafers Fabrication with Double Side Hybrid Bond Pads for Chip Stacking

3D packaging with stacked dies is widely explored as a future advanced packaging technology for applications involving high-performance computing and High Bandwidth Memory (HBM) devices. In this direction, chip-to-wafer (C2W) hybrid bonding is an emerging technology that offers high I/O and heterogeneous integration of chips. For HBM stacking, the hybrid bond pads need to be fabricated on both sides. The backside process involves the wafer going through a temporary bonding and debonding (TBDB) process, and thus, the thermal budget of the fabrication processes is limited up to 200 °C. Therefore, a low-temperature PECVD-deposited SiCN was evaluated as the dielectric material for backside fabrication. This article focuses on the process challenges and mitigation plans in thin Wafers fabrication on 300 mm silicon wafer using the revised integration flows to enable four to eight memory chip stacking.