Copper has emerged as the leading candidate for the next off-chip interconnection node, effectively addressing the evolving demands for pitch scalability, power handling, and thermal stability in future high-performance electronic systems. Although hybrid bonding is a well-established technology at the foundry level, it faces limitations at the package level due to process-material incompatibilities, thermal budget constraints, and difficulties in managing the increased non-coplanarity expected in substrate manufacturing. To overcome these challenges, our team has pioneered the use of nanoporous-Cu (NP-Cu) – a compliant, highly reactive bonding interface material. We have demonstrated the potential of this technology in achieving shear strength, electromigration performance, and reliability comparable to bulk-Cu interconnections formed by thermocompression bonding. However, NP-Cu bumps may experience varying bonding pressures locally during the assembly process due to flatness variations, necessitating a deeper understanding of the impact of non-coplanarities on the final microstructure, density, and properties of sintered NP-Cu joints. Addressing this question, an initial experimental and finite element modeling study assesses the effect of the initial mechanical properties of NP-Cu bumps on assembly height tolerance. The results indicate that bumps with an initial relative density of 40-60% can accommodate micron-scale non-coplanarities with bonding pressures of less than 50 MPa. The microstructure of NPCu bumps sintered under different loading conditions is then analyzed using focused-ion beam and scanning electron microscope to determine their final relative density. While pressure-assisted sintering predictably increases relative density, a pressure-less post-annealing step is found to be sufficient for achieving uniform microstructure and properties. Consistently achieving sintered NP-Cu interconnections with over 95% final densities is possible with bonding pressures of less than 50 MPa, underscoring the promise of this technology in providing a manufacturable solution to all-Cu interconnections in chip-to-substrate architectures.
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Amirnasiri et al. (2024) studied this question.
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