Silent Data Corruption from Timing Marginalities Due to Process Variations

We make the case, supported by recently published industrial data, that many of the hard to detect failures that escape post manufacturing tests and contribute to silent data corruption are timing failures resulting from significant increases in the delay of random circuit paths caused by manufacturing process variations. However, these are challenging to target at test because high coverage scan path delay tests are impractical. This research is investigating the characteristics of extreme statistical outlier slow paths in circuits with the goal of finding alternate test methods to detect and screen them out. We are particularly focused on low voltage operation because circuit delays due to process variations are greatly accentuated in that environment. A significant observation from this research is that delay increases from variability are not uniformly distributed among the gates in a potentially failing slow path. Instead, most of the delay increase is concentrated in a single gate. This suggests that node oriented TDF timing tests may remain at least partially effective in detecting many of the timing failures caused by process variations. We show how the test voltage and clock timing of the applied TDF scan tests can be optimized to enhance the likelihood of detection of these marginal timing parts.