A Partition-Aware VNF Placement Methodology for FPGA-Equipped NFVIs

In the context of Network Function Virtualization (NFV), Field Programmable Gate Arrays (FPGAs) can be used to reduce bottlenecks introduced by the substitution of dedicated hardware middleboxes by virtualized implementations. The problem of placing Virtualized Network Functions (VNFs) on FPGA-equipped NFV infrastructures, however, imposes additional challenges that require an accurate modeling of the FPGA fabric. More specifically, simultaneous sharing of the FPGA requires careful partitioning of its resources into fixed regions that can be dynamically reconfigure and to which functions can be mapped. In this work, we will demonstrate that accurate modeling of the FPGA partitions into the placement solution is crucial to achieve solutions that are guaranteed to be viable. Experimental results obtained through two Integer Liner Programming models will be used to demonstrate that partition awareness can avoid invalid solutions caused by overestimation of the device capabilities, with a small impact on the number of allocated user requisitions.