Analysis of Different LFSRs for VLSI IC Testing

This paper presents a Verilog-based design and comparative analysis of Linear Feedback Shift Registers (LFSRs) for VLSI testing. Various LFSR types, such as Galois, Bit Swapping, and Bit Reversal, were studied, including their implementations, feedback tap designs, and polynomial degrees. Using Verilog HDL and Xilinx ISE Vivado ML Standard Edition, these LFSRs were simulated and synthesized. The study embeds the LFSR unit into the tested circuit, using pseudo-random patterns to detect stuck-at-faults. Comparison criteria include test pattern quality, area, and power consumption. NIST Statistical Test Suite has been run on the generated test vectors to evaluate their randomness. The performed analysis shows that optimised design of Bit Reversal Architecture proved the most efficient when we talk about the number of clock cycles required to generate the test patterns required. With the power consumption point of view, it showed a 4 % decrease in signal power but a 17.39 % increase in logic power. The work concludes that LFSR selection should align with application needs, highlighting the significance of comparative analysis for optimal LFSR choice in specific applications.