Circuit Techniques for High Performance in CDDK Domino Logic

The designing of digital systems requires a circuit topology that is high-speed, robust, and power-efficient. To improve performance, several domino logics structures have been proposed in the literature to address the issues such as leakage current, power consumption, charge sharing, and robustness. In this paper, methods are presented to improve the speed and/or power of Clock-Delayed Dual-Keeper (shortly called CDDK) Domino circuits. This paper focus on two aspects of improving the performance such as: (i) by providing conditional additional discharge path and (ii) using multi-threshold transistor technique. The designs and evaluations of the circuits have been conducted, performed using Cadence® Virtuoso with additional features like ADEL and ADEXL with technology library of 90nm, and the results and analysis of simulating OR gate which consists of 8-inputs showed that the CDDK circuit which is having an additional discharge path resulted in a 12% increase in speed and the CDDK circuit with Multi-Threshold CMOS transistor resulted in a 44% decrease in power when compared to conventional domino logic circuits consists of Clock-Delayed Dual Keeper.