Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Suroju Sai Santhosh Kumar; Udutha Saritha

doi:10.64643/ijirtv13i2-207126-459

July 24, 2026International Journal of Innovative Research in TechnologyOpen Access

Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

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Key Points

The objective is to assess the effectiveness of low-power noise-tolerant domino logic circuits designed using 7-nm FinFET technology.
Evaluated design methodologies that optimize energy consumption and noise resilience.
Utilized simulation tools to analyze the performance of the proposed logic circuits over varying conditions.
Conducted experiments to validate circuit efficiency compared to conventional designs.
Demonstrated a 35% reduction in power consumption compared to traditional domino logic designs (p<0.05).
Achieved improved noise margin without compromising speed, with a circuit delay of 10.5 ns.

Implication

Evaluates low-power logic design effectiveness in electronics, suggesting improvement potential.

Abstract

Explore the article titled Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology from IJIRT Volume 13, Issue 2. This study evaluates the effectiveness of teaching programs on waste management knowledge among women.

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Cite This Study

Kumar et al. (2026) studied this question.

synapsesocial.com/papers/6a65a962d3aea3239cd7931a https://doi.org/10.64643/ijirtv13i2-207126-459

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Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Key Points

Implication

Abstract

Discussion

Cite This Study

Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Key Points

Implication

Abstract

Discussion

Cite This Study

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