Implementation and Evaluation of SIMD Instructions using RISC-V

This thesis introduces and explores the design and verification of a packed Single Instruction, Multiple Data (SIMD) instruction set for a RISC-V processor, known as the RISC-V P extension. This extension enhances the RISC-V instruction set architecture by providing packed SIMD support for 8-bit, 16-bit, and 32-bit integer data types. The significance of this architecture lies in its potential to empower developers in constructing more efficient and powerful data-parallel programs for RISC-V processors. This contribution enhances the overall capabilities of the RISC-V ecosystem, providing a valuable extension to the instruction set architecture for data-parallel applications.