Scheduling Semiconductor Manufacturing Operations in Research and Development Environments

This paper focuses on a scheduling problem encountered in shop floors of Research and Development (R&D) semiconductor manufacturing facilities. R&D facilities are characterized by a large product mix in very small quantities with unique/non-standard/varying processing routes, little process control of engineering experiments, dynamic prioritization of research activities, and pre-process checks. In contrast to typical scheduling problems found in semiconductor manufacturing systems, we provide and discuss the implications of factors of complexity (unknown parameters, evolving settings, R&D fab characteristics, etc.) on operations' scheduling specific to R&D environments. An existing dispatching rule-based heuristic, running in R&D settings, is challenged, investigated, and improved. Numerical experiments are conducted on a real-life instance and analyzed in terms of: (i) the sequence performance and quality, and (ii) the approximation accuracy of uncertain processing times and its impact on the decision performance.