A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

For low-power 8.5-Gbps operation, 4th-generation 10-nm 16-Gb LPDDR5x DRAM I/O circuits and control methods are proposed in this article. The proposed I/O improves signal integrity (SI) and power integrity (PI) by using a self-pre-emphasized stacked driver in transmitter (Tx), a supply voltage insensitive data receiver (Rx), and an optimized clock tree in write clock (WCK) clock paths. The measured eye widths of Tx and Rx, which are the indicators of the SI/PI, are 0.66 unit interval (UI) and 0.57 UI at 8.5 Gbps, respectively. Also, the measured power consumption is reduced by 20.0% compared to the previous LPDDR5 SDRAM product.