Lithography WEE, EBR and Pre-SiGe HF Clean Flow Rate Optimization for Wafer Edge Defectivity Improvement

Defects on wafers have always been a major concern in wafer fabrication processing. Most defect optimization activities centered around improving wafer front side defects by having more-clean steps, process chamber controls, process recipe improvements etc. However, there is minimum focus and attention on wafer edge bevel defects due to the lack of suitable equipment and detection methods and lack of skills and knowledge about their origin and effects. These defects can impact yield performance, cause wafer scrap, and even impact equipment uptime and higher costs due to machine faults and reworks. Often a series of cleaning and defect scanning equipment is needed that can easily cause a day or two days loss of cycle time. In this paper, we focus on how the defects are transported to the wafer frontside from the wafer's edge bevel and a provide a new understanding on how to reduce wafer edge defects from the wafer bevel by focusing on the process steps that cause defect formation.