Elimination of Bond Pad Etch Induced Wafer Arcing via Reducing ESC Chuck Surface Charges

DRAM wafers had frequent arcing events in a bond pad etch process, which resulted in severe yield loss, unscheduled down time, and associated cost due to part cleaning and replacement. The arcing was found to occur on wafers only at mirror position of upper I electrode pressure gauge port location. We have identified higher ESC chucking voltage and exposed Al at upper electrode as the main root causes for the arcing. A new baseline bond pad etch recipe with reduced ESC chucking/de-chucking voltage combined with a new recoating Y <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> coating procedure has been developed. With implementing this new baseline process, we have eliminated arcing events by 98%, improved unscheduled downtime of tools by 1.2% for maxing out production throughput, and reduced yield loss significantly.