Elimination of Pinhole Defects in Self-Aligned Double Patterning Process by using Bias Pulsed Plasma

Self-aligned double patterning (SADP) is extensively utilized in advanced sub-20nm technology nodes. The DRAM digit contact SADP dry etch process experienced severe yield loss due to pinhole defects in the periphery. The root cause was identified through etching characteristics analysis to be the micro-loading effect between the dense/isolated areas and non-uniform etching from center-to-edge of the wafer. Using the design of experiment model, a new recipe has been developed to eliminate pinhole defects by optimizing bias pulsing and pressure. This approach has led to a 50% improvement in etching uniformity and better etching selectivity. The proposed recipe has effectively eliminated pinhole formation, significant improving pinhole-related yield loss from 0.3%-50% to zero.