Polysilicon is widely used as material for Emitter in vertical Bipolar Junction Transistors (BJT) to obtain high current gain (Beta). To optimize the electrical properties of polysilicon (Poly) Emitter BJTs, interface between the Emitter poly and the Base needs to be engineered carefully. This paper explains the sources and effects of interface oxide thickness variations in PNP transistors fabricated with polysilicon Emitter deposited by LPCVD furnaces. By growing a thin layer of chemical oxide at the interface prior to the deposition of polysilicon, a controllable, repeatable, and uniform layer of interface oxide is achieved, giving a stable and consistent electrical performance across all furnace boat positions.
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Dineshan et al. (2024) studied this question.
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