The Influence of Interface Modification and Etched SiO

This study proposes a strategy that integrates the collaborative optimization of Etched SiO2 Layers with interface modification, and systematically examines the effects of the etching process, OTS (octadecyltrichlorosilane) modification layer, and PFBT (pentafluorobenzenethiol) modification layer on the performance of bottom-gate-bottom contact (BC-OFET) devices. A continuous planar electrode structure was constructed via 30-second wet etching. In conjunction with OTS/SiO2 interface modification and PFBT/Cu electrode modification, dual enhancements in carrier transport efficiency and photosensitive characteristics were achieved. The results indicate that: the carrier mobility of the optimized device increased from 1.05×10-3 cm²/V·s to 6.36×10-3 cm²/V·s (a 6.06-fold improvement), the threshold voltage decreased from -25V to -16V, the external quantum efficiency (EQE) reached 564.54%, and the photoresponsivity (R) increased to 2.95A/W. The light-dark current ratio reached 2.00. Research demonstrates that the etching structure eliminates the step difference between the electrode and dielectric layers, OTS enhances the quality of semiconductor crystallization, and PFBT improves the matching of electrode work functions.