Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F² DRAM Below Equivalent 10nm Node

DRAM scaling is pivotal for big AI computing era, with 3D stackable DRAM [1]-[3] considered a solution in the future. Positioned between conventional 2D DRAM and future 3D DRAM, the 4F 2 DRAM [4] is an attractive candidate. In this work, we propose a stacked 4F 2 DRAM with circuit under array (CuA) to enhance the memory density. To avoid new channel material complexities, we propose adopting an annealed poly-Si channel access transistor (akin to [5]), with an additional auxiliary gate (AG) to minimize the GIDL leakage current. Results show that the Si-based channel material with gate-all-around (GAA) transistor can achieve ultra-low leakage current ~0.33fA at drain bias =1V, supporting >10sec retention with a 7fF cell capacitance. No floating-body effect or Vt instability is observed for the nano-wire fully-depleted GAA device. The proposed stacked 4F 2 DRAM with CuA holds potential for equivalent <10nm node DRAM. The CuA process offers an opportunity to boost internal bandwidth by designing numerous small tiles for maximum parallelism, making it a promising advancement in the realm of DRAM scaling for the AI era.