Implementation Of RISC-V ISA in Verilog for low power consumption using clock gating techniques

Over the recent years RISC-V has become one of the most trending topics in the technology released in the year 2010 at University of California, Berkeley it open and free standard which anyone can pickup, design their own processors without any fear of restrictions about licenses or royalties.Design and innovate any core that fits their product like never before and probably used a lot in artificial intelligence, IOT, Medical devices, wireless communication, phones and other applications in future.In this paper we tried to study and implement low power single cycle RISC-V ISA using negative latch clock gating technique, where we have implemented subset of 64-bit RV64I instructions from R-Type, I-Type, S-Type and B-Type in Verilog realized in FPGA and verified its working by doing simulations in modelsim for various instructions and then doing synthesis in vivado 2023.1 checking the power and its resource utilizations.