This work presents a sixth-order partially time-interleaved bandpass delta-sigma modulator (BP DSM) for direct intermediate-frequency (IF) digitization. There are three resonators, and each of them is built with a passive <tex-math notation="LaTeX">N</tex-math> -path filter; while two open-loop operational transconductance amplifiers (OTAs) are inserted in between to realize the loop filter. The partially time-interleaved implementation enables a wide IF tuning range from 125 to 600 MHz. Besides, the OTAs are free of bandwidth limitation by deploying their equivalent large output resistors as the input resistors of the load <tex-math notation="LaTeX">N</tex-math> -path filters. Therefore, the BP DSM is power-efficient without compromising its performance. As a validation on the design, a prototype is fabricated in a 65-nm general-purpose (GP) CMOS technology. For a fixed 2-MHz bandwidth, the prototype achieves over 70-dB signal-to-noise-and-distortion ratio (SNDR) from 150-to 250-MHz IF; and it achieves over 60-dB SNDR from 125-to 550-MHz IF. The prototype achieves a peak SNDR of 72.0 dB and a maximal dynamic range (DR) of 75.1 dB at 150-MHz IF, while dissipating only 0.42 mW (including the clock generator) from a 1-V supply. This results in a Walden's figure of merits (FoM) of 32.3 fJ/conversion-step and a Schreier's FoM of 168.8 dB.
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Jin et al. (2024) studied this question.
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