Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits

This study investigates the timing margin required to handle fluctuations and variations in superconductor single-flux-quantum gate-level-pipelined adders; a smaller timing margin would improve the clock frequencies of gate-level-pipelined circuits. To evaluate timing margins, we demonstrated three 4 bit adders with 50-, 75-, and 100 GHz target clock frequencies using a 1.0 μ m process. We estimated that the required timing margin of the adders was 2.1 ps. This indicates that previously reported gate-level-pipelined circuits operating at 30–60 GHz could operate at higher clock frequencies by reducing the timing margins.