Understanding Microbenchmark Detection of Existing Exploits in Apple M1 and M2 Chips

Understanding the causes, effects, and detection / mitigation methods of side-channel attacks (SCAs) is essential in providing a secure environment. Current studies into SCAs have focused on Intel microarchitecture and Apple Silicon chips (such as M1 and M2) have been left under-represented in the research literature. The aim of this paper is to identify a gap in microarchitectural research of M1 and M2 Apple chips. The long-term objective of this research is to apply the Unified Side Channel Attack - Model (USCA-M) four-phase testing process to identify the critical components used within the exploit and at a low-level catch the Hardware Performance Counter (HPC) events of M1 and M2 chips.