Design and Implementation of a Low Power Arithmetic and Logic Unit for MIPS32 Processor

Today's technology is around designing low power electronic devices. Thus, to address the challenge, this paper introduces a novel clock gating approach targeting the arithmetic and logic unit (ALU) within high-performance processors. Leveraging the MIPS32 (Microprocessor without Interlocked Pipeline stages) architecture, we employ a latch-based clock gating technique implemented on the Xilinx Vivado platform using Verilog HDL, showcasing its practical applicability. Our method effectively reduces total thermal power dissipation, demonstrating a significant reduction of approximately 16%. This research underscores the importance of computational power and energy conservation in microprocessor architecture design. Through systematic experimentation and analysis, our findings highlight the efficiency of latch-based clock gating techniques in addressing power dissipation challenges, offering promising avenues for future advancements in microprocessor design.