Design and Comparative Analysis of Clock-Gated and Power-Gated 8-bit ALU for Low-Power VLSI Applications

This work presents the design and comparative analysis of an 8-bit Arithmetic Logic Unit (ALU) implemented using clock gating and power gating techniques for low-power VLSI applications. The ALU is designed to perform 8 arithmetic and 8 logic operations including addition, subtraction, AND, OR, XOR, and NOT operations. The proposed design is implemented in Verilog HDL and simulated using Xilinx Vivado. Comparative analysis is performed between conventional ALU, clock-gated ALU, and power-gated ALU in terms of power consumption, delay, and area utilization. Results show that power gating achieves up to 40-45% reduction in leakage power compared to conventional design, making it suitable for battery-operated and IoT devices. Keywords: ALU, Clock Gating, Power Gating, Low Power VLSI, Verilog HDL, Xilinx Vivado, Power Optimization Project by:- Randive Abhijeet Santosh- Sadaphal Harshal Ravindra - Shinde Prashant ShantaramUnder guidance of Prof. Bugade PrajaktaDepartment of Electronics and Telecommunication EngineeringJaihind College of Engineering, KuranSavitribai Phule Pune University, 2025-26