An Eight-Term Karatsuba Multiplier for Cryptographic Hardware Primitives on FPGAs

It is essential to have efficient large integer multiplications for current cryptosystems. Karatsuba-like multiplication is one of the most efficient multiplication algorithms, but is mostly avoided due to complex sub-multiplications. Thus, efforts has been made to implement eight-term Karatsuba Multiplication (Method-II), i.e., ETKM-II in terms of speed and hardware utilization. The overall performance of the proposed design methods are noted by calculating Area-Time-Product (ATP) and compared with conventional eight-term Karatsuba multiplication (CETKM) and existing state-of-the-art. Hardware implementations of the proposed ETKM multiplication architectures are done using Virtex-7 FPGA device in Xilinx ISE platform. Compared with other state-of-the-art designs the performance of the proposed eight-term Karatsuba multiplication (MethodII) based on Δ ATP₂ is 13.396%, 78.206% and 38.740% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM) and CETKM respectively for 1024bit inputs. However comparing the proposed ETKM-II, it can be inferred that ETKM-II is 38.740% better than CETKM thus proving its area-time-product efficiency.