Comparative Assessment of Charge Sharing and Charge Coupling Circuits: An Approach for Optimal In-Memory Computing

This study investigates and compares the energy efficiency, signal delay, Energy-Delay Product (EDP), and Power-Delay Product (PDP) characteristics of two widely used charge storage and transfer techniques: charge sharing and charge coupling, within the context of memory computing cells. The aim is to identify the most suitable circuit for facilitating Multiply-Accumulate (MAC) operations crucial for tasks such as matrix multiplications with predefined weights in neural networks. Our research reveals that in a typical memory computing cell scenario, charge sharing dissipates approximately 613.3 fJ of energy with an average power of 14.88 μW and a delay of 2.631 ps, resulting in a PDP of 39.149 aJ, while charge coupling consumes only 4.806 fJ with an average power of 8.794 μW and a delay of 3.339 ps, resulting in a lower PDP of 29.363 aJ. Furthermore, the study analyzes the advantages and limitations of both methods, considering their applicability in memory computing cell-based circuits. By providing insights into the performance metrics and practical implications of charge sharing and charge coupling techniques, this research aims to inform decision-making in selecting the most effective charge storage and transfer technique for memory computing cells, thus facilitating improved MAC operations and bolstering capabilities for data-intensive applications at the edge.