Design of Ferroelectric Field-Effect Transistor (FeFET)-Based Computing-in-Memory Architecture with Energy-Efficient and Low Latency for Edge AI Computing

The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel ADC-free CiM architecture based on Ferroelectric Field-Effect Transistors (FeFETs). Logic circuits (NOR, NAND, XNOR) that store weight vectors within FeFETs were designed. Compared with analog CiM circuits, the FeFETs-CiM circuits proposed in this paper can reduce power consumption by 901.1 times and latency by 272.7 times. Furthermore, the design of 3-bit FeFETs-CiM gates was extended, demonstrating flexible configurability for scalable edge computing applications. Finally, an application specific FeFETs-CiM subtractor for k-nearest neighbor (kNN) distance calculation was designed, which energy consumption is as low as 85.02 fJ/OP and latency is as low as 0.56 ns under 500 MHz operation frequency. The calculation robustness of the FeFETs-CiM kNN distance calculator was ensured by simulating under different process corners and temperatures. The performance improvements owing to the proposed FeFETs-CiM CMOS circuits were evaluated by taking the kNN algorithm as an example, which can ensure the data access reduction by more than 300 times compared to von Neumann architecture.