Circuit simulation study demonstrates pipeline-style FeFET logic-in-memory cuts energy consumption by 45–50% over CMOS latches, suggesting a pathway to overcome von Neumann architecture bottlenecks.
Emerging non-volatile (NV) memory devices provide the bases for innovative solutions to overcome the limitations of the Von Neumann architecture. Hafnium oxide-based ferroelectric field-effect transistor (FeFET) is considered the most competitive one among the promising devices. This research introduces an FeFET based design approach for Logic-in-memory (LiM) circuits, which is based on proposed basic arithmetic circuits, a dual-module multiplexing accumulator and a dual-module multiplexing multiplier. The proposed design methodology not only significantly enhances energy efficiency but also substantially improves data processing capabilities. Simulation results show that under the same conditions, the FeFET-based three-stage pipeline circuit uses 45–50 % less energy and completes tasks 1.5 clock cycles earlier than the traditional CMOS latch-based design. Furthermore, the proposed FeFET-based accumulator and multiplier consume 25–30 %, 5–10 % less energy respectively and work twice as fast as previous designs.
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Li et al. (2025) studied this question.
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