A calibration-free 12-bit 100-MS/s pipelined-SAR ADC with a gain-boosted residue amplifier using transient-current boosting in 65-nm CMOS

This paper presents a calibration-free 12-bit 100-MS/s two-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) fabricated in 65-nm CMOS. An 8 × closed-loop residue amplifier (RA) comprising a gain-boosted folded-cascode first stage and a current-reuse inverter-based second stage is employed for accurate residue amplification. Transient-current boosting temporarily increases the second-stage output drive during initial large-signal settling and is subsequently disabled during fine settling. Post-layout simulations show that the boosting reduces the upper bound on the settling time from 4.5 to 3.5 ns for a 0.4-V differential output swing, providing at least 1.5 ns of margin within the 5-ns amplification interval without increasing the nominal quiescent current. The core amplifier achieves a minimum simulated open-loop dc gain of 89.1 dB and a minimum unity-gain frequency of 1.94 GHz. The 2-bit interstage redundancy and nonbinary second-stage conversion provide tolerance to bounded comparator-decision and CDAC-settling errors, while no interstage-gain or bit-weight calibration is employed. At 100 MS/s, the prototype achieves measured SNDRs of 67.45 dB at low input frequency and 66.38 dB near Nyquist, corresponding to ENOBs of 10.91 and 10.73 bits, respectively. The ADC core occupies 0.175 mm 2 . The total power consumption is 3.98 mW, yielding a Nyquist Schreier figure of merit of 167.4 dB.