A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

1. 1An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS2008 · 191 citations
2. 2A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS2010 · 50 citations
3. 3A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s2010 · 439 citations
4. 4Ring Amplifiers for Switched Capacitor Circuits2012 · 241 citations
5. 5A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure2010 · 1,285 citations