This article presents a 13.7–41 GHz ultra-wideband frequency doubler with high efficiency and conversion gain (CG). The proposed cross-coupled push-push structure, in conjunction with the fourth-order transformer-based resonator and the series gate inductor, collaboratively shapes the input signal amplitude such that three distinct peaks emerge at different frequencies, thereby significantly improving the bandwidth. By introducing the resistorRCand inductorLSinto the proposed cross-coupled structure, the in-band flatness can be finely tuned with minimal impact on the frequency of the third peak, thereby offering an additional degree of freedom for flatness optimization. To improve the second harmonic output power and efficiency, a st acked common-gate amplifier is introduced. Furthermore, a coupled-inductor-based output matching network is designed to further extend the bandwidth to low frequencies. Fabricated in a 40 nm CMOS process, the proposed frequency doubler achieves a3-dB bandwidth of 27.3 GHz (fractional bandwidth of 99.8%), a 1.5-dB bandwidth of 24.5 GHz (fractional bandwidth of 91.6%), and a peak CG of −2.7 dB at an input power of 3 dBm. The measured saturated output power is 7 dBm, with a peak drain efficiency of 14.1% and a peak total efficiency of 10.6%. Across the entire bandwidth, the fundamental harmonic rejection ratio (HRR) and the third HRR are greater than 21.3 and 35.6 dBc, respectively.
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Li et al. (2026) studied this question.
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