A resource-efficient Arbiter PUF resilient to machine learning attacks leveraging the Strict Avalanche Criterion

Physical Unclonable Functions (PUFs) provide hardware-rooted security for resource-constrained devices by generating large numbers of challenge–response pairs (CRPs). However, conventional Arbiter PUFs (APUFs) are vulnerable to machine learning (ML) attacks because of their approximately linear challenge–response relationship. This work presents a Strict Avalanche Criterion (SAC)-enhanced APUF architecture comprising two lightweight modules. The first module extracts dual-path process variations and maps them to dynamically reconfigurable Linear Feedback Shift Register (LFSR) taps, thereby introducing nonlinearity into challenge generation. The second module combines multiplexers (MUXs) and XOR gates to provide response confusion and security post-processing. FPGA experiments against four representative ML attacks show that, even with 1,000,000 CRPs, all prediction accuracies remain below 60%, close to the ideal random-guessing rate of 50%. The proposed design achieves this ML resistance using only 142 LUTs and 70 FFs.