A 20-MS/s 13-bit pipelined SAR ADC with two-phase floating inverter amplifier

This paper presents a calibration-free, low-power, high-linearity 20-MS/s 13-bit pipelined successive approximation register (Pipelined SAR) analog-to-digital converter (ADC). A novel two-phase floating inverter amplifier (TPFIA) is proposed, which enhances the open-loop gain of the FIA by 22 dB while maintaining excellent linearity. This design achieves a precise inter-stage gain of 16x, thanks to the advantages of high linearity and high gain. The prototype ADC simulated in a 65 nm CMOS process, demonstrates an SNDR of 75.88 dB and an SFDR of 103.08 dB at 20 MS/s without the need for inter-stage gain calibration techniques or common-mode feedback (CMFB) circuits. The proposed amplifier consumes only 88.39 μA from a 1.2-V supply, leading to a Schreier figure-of-merit (FoM S ) of 179.32 dB.