A 72-Gb/s/pin PAM-3 transmitter with asymmetric reconfigurable feedforward equalizer and edge-shaping crosstalk cancellation

This work presents a 72-Gb/s three-level pulse amplitude modulation (PAM-3) transmitter (TX) implemented in 28-nm CMOS technology. To enhance signal integrity, the TX implements an asymmetric reconfigurable feedforward equalizer (AR-FFE), which consists of a configurable FFE and a booster. The booster is activated during major symbol transitions, dynamically enhancing the signal amplitude and mitigating inter-symbol interference (ISI) where additional bandwidth is required. The proposed architecture achieves a 60% improvement in total eye area compared to conventional FFE schemes. The TX integrates an edge-shaping crosstalk cancellation (ES-XTC) circuit to suppress far-end crosstalk (FEXT) from adjacent channels. The ES-XTC circuit utilizes look-ahead logic to synthesize cancellation pulses with programmable polarity and weight, adaptively suppressing FEXT based on the aggressor’s data. The simulation results show that at a data rate of 72 Gb/s, the TX achieves an energy efficiency of 0.93 pJ/bit, and a cross induced jitter (CIJ) reduction of 0.49 UI, indicating its potential for next-generation high-speed chiplets and memory interconnects.