A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for 4× 24 Gb/s/Pin Single-Ended DRAM Interface

A crosstalk compensation (XTC) receiver is proposed for a single-ended four-level pulse amplitude modulation (PAM-4) signaling DRAM interface. The receiver compensates for the crosstalk from two adjacent pin signals by using an RC circuit per pin. The transmitter of the test chip consists of a voltage-mode PAM-4 driver and a three-tap feed-forward equalizer. The XTC circuit at the test chip receiver consists of six blocks of a current-integrating differential amplifier per pin. The current integrating differential amplifier includes three differential pairs, one for its own pin data and the other two for adjacent pin data. The test chip, fabricated on a 28-nm CMOS low-power process, worked successfully at a data rate of 24 Gb/s per pin with four parallel 5-cm long microstrip lines on an FR-4 printed circuit board. The width was 14-mil and the center-to-center spacing was 35-mil. Compared to the previous crosstalk compensation scheme that uses three or more multi-pins, each with one RC circuit and two CR circuits per pin, the transmission coefficient at the receiver input pin was enhanced by 1.31 dB from –1.89 dB to –0.58 dB at the Nyquist frequency of 6 GHz. The XTC circuit opened the closed eyes of both the second and the third pin data among the four data pins of the test chip to 0.12 UI at 24 Gb/s per pin with PAM-4 signaling and bit error rate of 10 <tex-math notation="LaTeX">⁻¹²</tex-math> . The energy efficiency of the receiver test chip was 1.28 pJ/bit at the 1.1 V supply.