What question did this study set out to answer?

To develop a high-speed, single-ended PAM-4 transmitter for memory interfaces that mitigates far-end crosstalk and switching jitter without degrading output signal swing or bandwidth.

December 9, 2024IEEE Journal of Solid-State Circuits

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS

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Authors

WWWU Weitao HWHongzhi Wu LZLiping Zhong

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Overview

Experimental evaluation demonstrates a 64 Gb/s single-ended PAM-4 transmitter with 82% jitter reduction, suggesting improved bandwidth and energy efficiency for dense memory interfaces.

Key Points

To develop a high-speed, single-ended PAM-4 transmitter for memory interfaces that mitigates far-end crosstalk and switching jitter without degrading output signal swing or bandwidth.
Fabricated a single-ended PAM-4 transmitter in 28-nm CMOS featuring a merged preemphasis capacitive-peaking crosstalk cancellation scheme.
Integrated a 3-tap reconfigurable fractional-spaced feed-forward equalizer with a predriver coefficient selector to avoid extra driver cells and lower parasitic capacitance.
Evaluated high-speed data transmission and jitter metrics under an insertion loss of −11 dB and far-end crosstalk of −15.8 dB at 16 GHz.
Achieved a 64 Gb/s transmission speed with an energy efficiency of 1.27 pJ/bit.
Reduced the crosstalk-induced jitter ratio by 82% using the merged capacitive-peaking crosstalk cancellation architecture.
Increased transmitter bandwidth by 60% through parasitic capacitance reduction via the predriver coefficient selector.

Cite This Study

Weitao et al. (2024) studied this question.

synapsesocial.com/papers/6a852bc622ea7ab258b2e84e https://doi.org/10.1109/jssc.2024.3509417

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December 9, 2024IEEE Journal of Solid-State Circuits

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS

View Full Paper

Ask AI

Bookmark

Authors

WWWU Weitao HWHongzhi Wu LZLiping Zhong

Discussion

Member takes

Overview

Experimental evaluation demonstrates a 64 Gb/s single-ended PAM-4 transmitter with 82% jitter reduction, suggesting improved bandwidth and energy efficiency for dense memory interfaces.

Key Points

To develop a high-speed, single-ended PAM-4 transmitter for memory interfaces that mitigates far-end crosstalk and switching jitter without degrading output signal swing or bandwidth.
Fabricated a single-ended PAM-4 transmitter in 28-nm CMOS featuring a merged preemphasis capacitive-peaking crosstalk cancellation scheme.
Integrated a 3-tap reconfigurable fractional-spaced feed-forward equalizer with a predriver coefficient selector to avoid extra driver cells and lower parasitic capacitance.
Evaluated high-speed data transmission and jitter metrics under an insertion loss of −11 dB and far-end crosstalk of −15.8 dB at 16 GHz.
Achieved a 64 Gb/s transmission speed with an energy efficiency of 1.27 pJ/bit.
Reduced the crosstalk-induced jitter ratio by 82% using the merged capacitive-peaking crosstalk cancellation architecture.
Increased transmitter bandwidth by 60% through parasitic capacitance reduction via the predriver coefficient selector.

Cite This Study

Weitao et al. (2024) studied this question.

synapsesocial.com/papers/6a852bc622ea7ab258b2e84e https://doi.org/10.1109/jssc.2024.3509417

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