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April 16, 2025IEEE Journal of Solid-State Circuits

A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS

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Authors

HWHongzhi WuXCXuxu ChengWWWU Weitao

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Overview

Experimental evaluation demonstrates a 128-Gb/s PAM-4 transmitter achieving 1.5 pJ/bit efficiency in 28-nm CMOS, indicating viable low-power ultra-high-speed wireline transceivers.

Key Points

  • To develop a high-speed, energy-efficient PAM-4 transmitter that minimizes switching jitter and maximizes output bandwidth in wireline communications.
  • Designed a current-mode transmitter integrating a pre-emphasis asymmetric fractional-spaced feed-forward equalizer (AFS-FFE) and an edge-boosting pulse generator.
  • Implemented a latch-minimized serializer that eliminates 4:1 multiplexer input-side latches in a 28-nm CMOS fabrication process.
  • The pre-emphasis AFS-FFE extended the minimum eye width by 67%, while the edge-boosting pulse generator increased transmitter bandwidth by 26%.
  • The latch-minimized serializer decreased transmitter data path power consumption by 36%.
  • Hardware measurements verified operation up to 128 Gb/s in both PAM-4 and NRZ modes with an energy efficiency of 1.5 pJ/bit.

Cite This Study

Wu et al. (2025) studied this question.

synapsesocial.com/papers/6aae4db3668337169243c138https://doi.org/10.1109/jssc.2025.3557781
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