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Experimental evaluation demonstrates a 128-Gb/s PAM-4 transmitter achieving 1.5 pJ/bit efficiency in 28-nm CMOS, indicating viable low-power ultra-high-speed wireline transceivers.
This article presents a 128-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter (TX) with a pre-emphasis asymmetric fractional-spaced feed-forward equalizer (AFS-FFE) and an edge-boosting pulse generator. The proposed pre-emphasis AFS-FFE mitigates unequal switching jitter (SWJ) in PAM-4 eyes, extending the minimum eye width by 67%. Additionally, the reconfigurable UI-spaced feed-forward equalizer (FFE) enhances the precision of the equalizer. The edge-boosting pulse generator accelerates the edge-transition speed of the driver’s output signal, increasing the TX’s bandwidth by 26%. Moreover, in the data path, the latch-minimized serializer eliminates 4:1 MUX input-side latches, thereby reducing the power consumption of the TX data path by 36%. Fabricated in a 28-nm CMOS process, measurement results show that the PAM-4 TX can operate in both PAM-4 and non-return-to-zero (NRZ) modes, achieving a maximum data rate of 128 Gb/s with an energy efficiency of 1.5 pJ/bit.
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Wu et al. (2025) studied this question.
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