A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

This is the authors' abstract. We don't add key points for this paper.

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver (TRx) designed in a 28-nm complementary metal-oxide-semiconductor (CMOS) process is presented in this article. A voltage-mode (VM) driver featuring a 4-tap reconfigurable feed-forward equalizer (FFE) is employed in the quarter-rate transmitter (TX). The half-rate receiver (RX) incorporates a continuous-time linear equalizer (CTLE), a 3-stage high-speed slicer with multi-clock-phase sampling, and a clock and data recovery (CDR). The experimental results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board (COB) assembly. The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV (upper-eye), 31 mV (mid-eye), and 28 mV (lower-eye) with an output amplitude of 353 mV single-ended. The recovered 14 GHz clock from the RX exhibits random jitter (RJ) of 469 fs and deterministic jitter (DJ) of 8.76 ps. The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ, at bit-error rate (BER) of 10 −5 (0.53 UI). The power dissipation of TX and RX are 125 and 181.4 mW, respectively, from a 0.9-V supply.