Fabrication of high-performance, sub-100 nm critical dimension vertical channel-all-around indium−gallium−zinc−oxide field-effect transistor and using for DRAM unit with optimized etching condition

This work fabricates a vertical channel-all-around indium−gallium−zinc-oxide field-effect transistor(CAA IGZO FET) through reasonable etching process and annealing optimization. The resulting device exhibits has a normalized on-current ( I ON ) of 87.1 μ A/ μ m, and a subthreshold swing (SS) of approximately 66.98 mV/Dec. These performance parameters are twice as good as similar work obtained in previous experiments, which is sufficient to meet the requirements for manufacturing 2T0C DRAM units. Moreover, with the double-layer stacking of this structure, the feasibility and scalability of manufacturing DRAM units with CAA IGZO FET is verified.