A 28-nm 2.25-Mb CO-DCIM RRAM Macro With 1.25-ns/bit Read Speed, 0.12-pJ/bit, and 12.85-Mb/mm 2 Storage Density for Autoregressive Transformer

Edge AI urgently demand computing hardware with large on-chip storage capacity, low memory access overhead. Resistive random-access memory (RRAM) based digital computing-in-memory (DCIM) suits such scenarios by achieving a optimized performance balance in calculation precision, storage density and access overhead. However, traditional RRAM-DCIM scheme suffers from two issues: 1) RRAM multi-bit storage boosts density but introduces significant errors, while conventional ECC scheme requires massive redundant bits that offset density gains; 2) Wiring RC parasitism in large-scale arrays leads to slow and energy-intensive random access. To resolve these issues, the proposed computation-oriented DCIM (CO-DCIM) paradigm integrates two core solutions: a hierarchical multi-bit storage coding scheme and a charge-domain continuous access scheme. The designed CO-DCIM macro is fabricated in a 28nm CMOS technology. Measurement results show a single RRAM read latency of 2.5 ns, normalized read energy of 0.12 pJ/bit, and a storage density of 12.85 Mb/mm2. The macro is further evaluated on public SimpleAR-0.5B-RL and SimpleAR-1.5B-RL workloads, showing a 29.2x reduction in mapped-weight access energy relative to LPDDR5X DRAM at256× 256resolution.