A High-Reliability and High-Performance Nonvolatile Magnetic Radiation-Hardened Latch Based on Approximate C-Elements

With the continuous advancement of transistor manufacturing processes, soft errors induced by space radiation particles have become a critical challenge in digital circuit design. This paper proposes a fully double node upset (DNU) tolerant nonvolatile magnetic (FDNUT-NVM) latch by using magnetic tunnel junctions (MTJs) and CMOS. DNU tolerance is provided by six cross-coupled PMOS dual-input approximate C-elements (PDACs) and a clock-gated three-input standard C-element (CG-TSC). Compared to the dual-input standard C-element (DSC), the PDAC reduces the number of transistors in the discharge path, thereby improving the speed and increasing the differential current. Furthermore, we propose an improved backup and restore module with higher reliability and lower power consumption than prior design. The proposed FDNUT-NVM latch achieves an optimal trade-off between speed and power consumption while maintaining high reliability. Using a physics-based STT-MTJ compact model and a commercial 40 nm CMOS design kit for simulations, the results show that under a tunneling magnetoresistance ratio (TMR) of 150% and a supply voltage of 1.2 V, the proposed FDNUT-NVM latch achieves a D-OUT delay of only 7.59 ps, a restore delay of 85.92 ps and a total power consumption of only50.48 \;μ W. Monte Carlo simulations further reveal that the error rate of restoration (ERR) from MTJs is as low as 0.7%. Moreover, the proposed FDNUT-NVM latch can fully tolerate DNU even in the worst case with a deposited chargeQᵢₙⱼof± 2 \;pC.