A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

This paper presents a 48-Gb/s quarter-rate four-level pulse amplitude modulation (PAM-4) receiver with a baud-rate clock and data recovery circuit. The modified time-interpolated latch (MTIL) is proposed to reduce the number of input comparators. The offset voltages of the comparators and the intersecting voltages of the MTILs are calibrated by using the foreground calibration. This PAM-4 receiver is fabricated in a 40-nm CMOS process and the active area is 0.089mm2. The power consumption is 62.8mW and the calculated energy efficiency is 1.31pJ/b. For a PRBS of 27-1, the bit-error rate is less than 10-12.