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April 17, 2024IEEE Transactions on Circuits & Systems II Express Briefs

A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches

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Authors

YHYuan-Pang HuangSLShen-Iuan Liu

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Cite This Study

Huang et al. (2024) studied this question.

synapsesocial.com/papers/68e6ecc0b6db643587667a74https://doi.org/10.1109/tcsii.2024.3390653
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  4. 4A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS2024
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