A 250-MS/s 8-b Cryo-CMOS SAR ADC for quantum computing in 65-nm technology

This paper presents a cryogenic 250-MS/s 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) prototype designed in 65-nm CMOS technology. A capacitive digital-to-analog converter (CDAC) employing a common-mode voltage split scheme and monotonic least-significant-bit (LSB) switching achieves reduced area and power consumption while maintaining stable top-plate voltage. Both a triple-latch feed-forward (TLFF) dynamic comparator and high-speed SAR logic are adopted to meet the stringent timing requirements imposed by the prolonged decision time at cryogenic temperatures. Furthermore, a robust clock receiver architecture is implemented with mitigated process, voltage, and temperature (PVT) sensitivity. These suitable circuit topologies mitigate performance shifts induced by cryogenic temperatures. Measurement results demonstrate that at 4 K, the ADC achieves differential nonlinearity (DNL) and integral nonlinearity (INL) within 0.8 LSB, with an effective number of bits (ENOB) exceeding 6.7 bits across the Nyquist bandwidth. The ADC core consumes about 1.31 mW, yielding a figure of merit (FoM) of 45.1 fJ/conversion-step, making it suitable for large-scale qubit readout.