Verification study demonstrates 100% functional coverage in a SystemVerilog UART design, indicating effective fault elimination through AHB verification IP.
Universal Asynchronous Receiver Transmitter is a serial communication protocol that helps in communicating data between devices. The verification of UART is important to eliminate any fault present in the design. In this paper UART module has been designed with transmitter UART and Receiver UART using System Verilog and the UVM based AHB Verification IP has been built to verify UART design. The coverage analysis block has been included in the test bench to analyze whether all the functionalities of the UART design has been verified. The functional coverage of 100% is achieved by using constrained random test with two test cases like half duplex communication mode an full duplex communication mode.
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D et al. (2024) studied this question.
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