Charge Trap Flash with Superior Program Efficiency by Negative Capacitance-Boosting Effect

The 3D NAND flash architecture has adopted the incremental step pulse program (ISPP) operation, involving the repetition of program (PGM) & read, with the aim of reducing the Vth variation. However, the repetitive PGM & read operations degrade the memory window (MW) and endurance properties of the charge trap flash (CTF) device. Thus, enhancements for MW and fast PGM speed are consistently desired. In this research, we report a high PGM efficiency and multilevel-cell CTF device using a negative capacitance (NC) effect in an imprinted antiferroelectric (I-AFE) and dielectric heterostructure blocking layer (BL). Enhancement of capacitance by the NC effect in our proposed CTF provides a high tunnel oxide field even at the same PGM voltage, thereby leading to a steep ISPP slope (~1.05), a large MW (>8 V), and robust endurance properties (>10 6 cycles). We found that, as for the BL, the accurate control of fixed charge at the top interface of the I-AFE and careful engineering of the flexoelectric effect using the high-pressure post-deposition annealing (HPPDA) process are crucial to enhancing the boosting effect. We expect that the NC-based functional BL plays an important role in advanced flash memory with superior performance.