Device Engineering and Benefit Maximization for Advanced Cryo-CMOS

Low temperature operation offers a reliable way for steep subthreshold slope (SS) with other benefits including higher mobility and drive current. In this work, we present characterizations for advanced FinFETs and embedded MRAM with the circuit analyses at reduced temperatures down to 77K. Steepened SS enables threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(VTH)</tex> and supply voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(VDD)</tex> scaling for ~0.27× power reduction without sacrificing logic switching speed. Improved gate dielectric reliability raises maximum <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDD</tex> for >70% speed boost. To further provide high-density MRAM for cryo- CMOS, the co-optimization for magnetic tunnel junctions (MTJs) and transistors is proposed to obtain high performance/high density cells. Benefiting from the higher thermal stability factor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(Δ =EB/KBT)</tex> and tunneling magnetoresistance ratio (TMR) of magnetic tunnel junctions (MTJs) at 77K, a higher cell density and improved read margins can be acquired in cryo-MRAM.