The future is frozen: cryogenic CMOS for high-performance computing

Low Temperature CMOS or Cryogenic CMOS is a promising avenue for continuation of Moore’s Law while serving high performance computing (HPC) needs. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With optimal threshold voltage engineering, the device ON current can be enhanced further, translating to higher performance. In this article, we use experimentally calibrated data to tune the threshold voltage and investigate the power performance area (PPA) of cryogenic CMOS at device, circuit and system level. We also present results from measurement and analysis of functional memory chips fabricated in 28nm bulk CMOS and 22nm FDSOI operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems will be discussed.