Material optimization of interconnects and transistors for energy-efficient and high-performance cryogenic GAA technology

Unprecedented computational demand is reshaping the landscape of energy-efficient and high-performance computing. As Moore’s law approaches its physical limits, continued progress to meet this demand can no longer rely solely on transistor scaling. Cryogenic operation of CMOS circuits offers a promising path forward, enhancing the subthreshold slope (SS) of transistors while enabling certain materials to exhibit superconductivity. This dual advantage positions device- and material-level optimizations as a compelling solution for next-generation cryogenic computing. In this work, we demonstrate that unlocking the full potential of cryogenic CMOS requires strategic transistor and interconnect-level optimizations. We show that (1) material optimization for tuning transistor work function is vital for translating SS improvements into a significant increase in ON current, while (2) exploiting superconducting interconnect materials at cryogenic temperatures is essential to eliminate resistive parasitics and overcome interconnect bottlenecks. To quantify these benefits, we employ a cryogenic-aware 2 nm gate-all-around nanosheet digital design flow, incorporating calibrated device models along with a full standard cell library. Our evaluation results targeting the compute fabric of the AI accelerator circuit demonstrate that our optimizations provide a 3× increase in TOPS, 7.7× increase in TOPS/W, and 23× improvement in efficiency TOPS 2 /W.