The rapid progress of smart sensors and biomedical front-ends is summoning high-precision, high-energy-efficiency ADCs. To be embedded-friendly, properties like easily driven, adaptive bandwidth, and feasible clock generation cost are also favorable. In recent years, noise-shaping (NS) SARs have gained a great vogue for their fully dynamic operation and high energy efficiency [1]–[3]. Although impressive performances have been realized, the input capacitors of previous >90dB SNDR NS-SAR works are 2.4pF~18pF to suppress kT/C noise at an OSR of 25~125 [1]–[2]. This poses a stringent requirement for the input and reference drivers at a sampling rate of several MS/s. The kT/C cancellation technique has been adopted to deal with this issue, but it needs another amplifier and complexes the timing sequence [3]. Continuous-time (CT) SAR ADC, which keeps track of the input signal by a capacitive input network, obviates the input sampling operation and transfers the real sampling to the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2ⁿᵈ</tex> stage input [4]. The comparison between DT SAR and CT SAR is shown in Fig. 1. Since the kT/C noise can now be suppressed by the inter-stage gain, the system SNR is no longer restrained by the input capacitance in CT SAR, which provides a direction to implement easy-driven high-precision NS-SAR ADCs.
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Meng et al. (2024) studied this question.
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