An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA

High-precision and ultra-low-power (ULP) ADCs have received significant demand recently due to their critical roles in biomedical or Internet-of-things products. However, achieving a 16-bit resolution with sub-micro-watt <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(< 1)</tex> ADCs remains a significant challenge, serving as a bottleneck for ULP signal acquisition systems. Noise-shaping (NS) SAR ADCs can effectively reduce in-band quantization noise and achieve high energy efficiency, potentially achieving ultra-low-power consumption. Pipelined versions of such ADCs using a residue amplifier (RA) further ease the design requirement of comparators and the backend stage, leading to a better solution for higher energy efficiency data conversion [1]. This work presents an ultra-low-power pipelined second-order NS SAR ADC with a high DC gain and energy-efficient RA, enabling the SNDR of 96.2dB and Schreier FoM (FoMs) of 180.8dB at only 871nW power consumption under 1.2V supply.